UNTRANSLATED .. 3.10

Clock Divider

Objective

Study of a clock divider, using a D flip-flop (TTL family, 7474).

Procedure

_images/clock-divider.svg

Discussion

The output toggles at every rising edge of the input, resulting in a division of frequency by two. The output is a symmetric squarewave, irrespective of the duty cycle of the input pulse. The HIGH output of the TTL IC is around 4 volts only.

_images/clock-divider.png _images/clock-divider2.png
Figure 3.1 A clock divider circuit, using a D-flipflop. Outputs for two different types of input are shown